1. Field of the Invention
The present invention relates to the technical field of boundary scan test interface and, more particularly, to an apparatus and method for accessing hidden data in a boundary scan test interface.
2. Description of Related Art
Since chip packages and multi-level printed circuit boards (PCBs) have become complicated more and more, the conventional in-circuit test using a bed-of-nail is not satisfactory as it is difficult to accurately contact the nodes on a PCB. In addition, due to the advance of surface mount technology (SMT), most ICs are mounted directly on the surface of a circuit board, which causes a problem that internal signals of the ICs cannot be tested directly. To overcome this, boundary scan technique has been developed. For example, the Joint Test Action Group (JTAG) boundary scan, formally known as IEEE-Std-1149.1, and IEEE1149.4 Digital Test Access Port interface, to define available boundary scan test interfaces for IC testing, which applies serial scan chain for testing the internal modules of an IC. FIG. 1 shows a block diagram of a typical JTAG interface. In FIG. 1, the JTAG interface uses five signal pins (TDI, TDO, TMS, TCK and nTRST) in scan chain data operation, i.e., TDI pin as a serial data input, TDO pin as a serial data output, TMS pin as a mode selection input, TCK pin as a clock input and nTRST pin as a system reset. As shown in FIG. 1, the JTAG interface includes a test access port (TAP) controller 11, a test data register 12, an instruction register 13 and a decoder 14.
The test data register 12 includes a scan chain register 121 as a scan chain to store serial data received by the TDI pin, an ID code register 122 storing special numbers to output, a bypass register 123 to directly forward the serial data from the TDI pin to the TDO pin for output.
The instruction register 13 stores a serial instruction received by the TDI pin. The decoder 14 decodes the serial instruction to thus control operations of the TAP controller 11.
The TAP controller 11 performs state transition based on the TMS pin's input and operates with the data of the register 12 and the outcome of the decoder 14. FIG. 2 is a state transition diagram of the TAP controller 11, where state transition occurs in sampling TMS signals at rising edges of a TCK signal output. As shown in FIG. 2, initially, the TAP controller 11 is at Test-Logic Reset state. Next, the controller 11 can enter states of idle process 21, data register process 22 and instruction register process 23. As TMS=1, the Test-Logic Reset state is unchanged, and when TMS=0, the state is transited to Run-Test/Idle state of the idle process 21. Next, the Run-Test/Idle state is unchanged as TMS=0, and transited to Select-DR-Scan state of the data register process 22 as TMS=1. In the Select-DR-Scan state, as TMS=0, the state is transited to Capture-DR state for processing of the register 12, and conversely, as TMS=1, the state is transited to Select-IR-Scan state of the instruction register process 23. In the Select-IR-Scan state, as TMS=0, the state is transited to Capture-IR state for processing of the register 13, and conversely, as TMS=1, the state is transited to the initial Test-Logic Reset state.
The aforementioned JTAG can transfer control signals or access registers through TDI and TDO pins for data read and write. However, data read and write through TDI and TDO pins are in sequential and can easily be detected. Thus, such secret register data cannot be protected. However, current processor development needs to protect equipment for development from steal by others. Therefore, it is desirable to provide an improved apparatus and method to mitigate and/or obviate the aforementioned problems.